ADT7463
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25
Figure 37. Understanding the THERM
Timer
THERM
ASSERTED
d22.76 ms
THERM
ASSERTED
e45.52 ms
THERM
ASSERTED
e113.8 ms
(91.04 ms + 22.76 ms)
THERM
THERM
THERM
TIMER
(REG. 0x79)
THERM
TIMER
(REG. 0x79)
THERM
THERM
TIMER
(REG. 0x79)
ACCUMULATE THERM
LOW
ASSERTION TIMES
ACCUMULATE THERM
LOW
ASSERTION TIMES
1
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
0
0
0
0
0
0
0
1
2
3
4
5
6
7
1
0
1
0
0
0
0
0
0
1
2
3
4
5
6
7
When using the THERM
timer, be aware of the following:
" After a THERM
timer read (Reg. 0x79):
1. The contents of the timer get cleared on read.
2. The F4P bit (Bit 5) of Status Register 2 needs to be
cleared (assuming the THERM
limit has been
exceeded).
" If the THERM
timer is read during a THERM
assertion,
then the following will happen:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM
timer is set to 1 (since a
THERM
assertion is occurring).
3. The THERM
timer increments from zero.
4. If the THERM
limit (Reg. 0x7A) = 0x00, then the
F4P bit gets set.
Generating SMBALERT
Interrupts from THERM
Events
The ADT7463 can generate SMBALERT
s when a
programmable THERM
limit has been exceeded. This
allows the systems designer to ignore brief, infrequent
THERM
assertions, while capturing longer THERM
events.
Register 0x7A is the THERM
Limit Register. This 8bit
register allows a limit from 0 seconds (first THERM
assertion) to 5.825 seconds to be set before an SMBALERT
is generated. The THERM
timer value is compared with the
contents of the THERM
limit register. If the THERM
timer
value exceeds the THERM
limit value, then the F4P bit
(Bit 5) of Status Register 2 gets set, and an SMBALERT
is
generated. Note that the F4P bit (Bit 5) of Mask Register 2
(Reg. 0x75) masks out SMBALERT
s if this bit is set to 1,
although the F4P bit of Interrupt Status Register 2 still gets
set if the THERM
limit is exceeded.
Figure 38. Functional Diagram of the ADT7463 THERM
Monitoring Circuitry
COMPARATOR
THERM
2.914 s
1.457 s
728.32 ms
364.16 ms
91.04 ms
45.52 ms
22.76 ms
182.08 ms
THERM
LIMIT
(REG. 0x7A)
2.914 s
1.457 s
728.32 ms
364.16 ms
91.04 ms
45.52 ms
22.76 ms
182.08 ms
THERM
TIMER
(REG. 0x79)
THERM
TIMER CLEARED ON READ
SMBALERT
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
CLEARED
ON READ
F4P BIT (BIT 5)
STATUS REGISTER 2
OUT
IN
RESET
LATCH
1 = MASK
0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
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